--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   11:11:53 01/22/2010
-- Design Name:   
-- Module Name:   C:/Custom32Processor/MySOC/TestCrtlUnit.vhd
-- Project Name:  MySOC
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ControlUnit
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- General package
use work.GeneralProperties.ALL;
 
ENTITY TestCrtlUnit IS
END TestCrtlUnit;
 
ARCHITECTURE behavior OF TestCrtlUnit IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ControlUnit
    Port ( memory_data          : in  STD_LOGIC_VECTOR ((bus_size-1) downto 0);
	        memory_data_out      : out     STD_LOGIC_VECTOR ((bus_size-1) downto 0);
           memory_read_address  : out    STD_LOGIC_VECTOR ((bus_size-1) downto 0);			  
           memory_write_address : out    STD_LOGIC_VECTOR ((bus_size-1) downto 0);
			  memory_read          : out    STD_LOGIC;
			  memory_write         : out    STD_LOGIC;			  
           CLOCK                : in     STD_LOGIC;
           RESET                : in     STD_LOGIC;
			  InImediate           : out    STD_LOGIC_VECTOR ((bus_size - 6) downto 0);
			  Flags                : in     STD_LOGIC_VECTOR (3 downto 0);
			  RegisterAValue       : in     STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
			  RegisterBValue       : in     STD_LOGIC_VECTOR ((bus_size - 1) downto 0);
			  SelMuxInput          : out    MultiplexSignals;
           SelAluOp             : out    ALU_operations;
			  SelShifterOp         : out    Shifter_operations;
			  RegFileWriteAddress  : out    ProcessorRegisters;
			  RegFileReadAAddress  : out    ProcessorRegisters;
			  RegFileReadBAddress  : out    ProcessorRegisters;
			  RegFileReadAEnable   : out    STD_LOGIC;
			  RegFileReadBEnable   : out    STD_LOGIC;
			  WriteRegistersFile   : out    STD_LOGIC;
           OutputEnable         : out    STD_LOGIC
			  );
    END COMPONENT;
    

   --Inputs
   signal CLOCK : std_logic := '0';
   signal RESET : std_logic := '0';
   signal Flags : std_logic_vector(3 downto 0) := (others => '0');
   signal RegisterAValue : std_logic_vector((bus_size-1) downto 0) := (others => '0');
   signal RegisterBValue : std_logic_vector((bus_size-1) downto 0) := (others => '0');
	signal memory_data : std_logic_vector((bus_size-1) downto 0) := (others => '0');

	--BiDirs
   

 	--Outputs
	signal memory_data_out : std_logic_vector((bus_size-1) downto 0);
   signal memory_read_address : std_logic_vector((bus_size-1) downto 0);
   signal memory_write_address : std_logic_vector((bus_size-1) downto 0);
   signal memory_read : std_logic;
   signal memory_write : std_logic;   
   signal InImediate : std_logic_vector((bus_size - 6) downto 0);
   signal SelMuxInput : MultiplexSignals;
   signal SelAluOp : ALU_operations;
   signal SelShifterOp : Shifter_operations;
   signal RegFileWriteAddress : ProcessorRegisters;
   signal RegFileReadAAddress : ProcessorRegisters;
   signal RegFileReadBAddress : ProcessorRegisters;
   signal RegFileReadAEnable : std_logic;
   signal RegFileReadBEnable : std_logic;
   signal WriteRegistersFile : std_logic;
   signal OutputEnable : std_logic;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ControlUnit PORT MAP (
          memory_data => memory_data,
			 memory_data_out => memory_data_out,
          memory_read_address => memory_read_address,
          memory_write_address => memory_write_address,
          memory_read => memory_read,
          memory_write => memory_write,          
          CLOCK => CLOCK,
          RESET => RESET,
          InImediate => InImediate,
          Flags => Flags,
          RegisterAValue => RegisterAValue,
          RegisterBValue => RegisterBValue,
          SelMuxInput => SelMuxInput,
          SelAluOp => SelAluOp,
          SelShifterOp => SelShifterOp,
          RegFileWriteAddress => RegFileWriteAddress,
          RegFileReadAAddress => RegFileReadAAddress,
          RegFileReadBAddress => RegFileReadBAddress,
          RegFileReadAEnable => RegFileReadAEnable,
          RegFileReadBEnable => RegFileReadBEnable,
          WriteRegistersFile => WriteRegistersFile,
          OutputEnable => OutputEnable
        );
 
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name     
 
   CLOCK_process :process
   begin
		CLOCK <= '0';
		wait for 100 ns;
		CLOCK <= '1';
		wait for 100 ns;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
		RESET <= '1';
      wait for 200 ns;
      
     	RESET <= '0';
      
      --wait for <clock>_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
